A New Delay Model for Distributed RLC Trees
نویسندگان
چکیده
In current VLSI circuits, interconnect delay dominates gate delay. As a result, high-level synthesis and physical layout tools are taking interconnect delay into account. Interconnects are generally in the form of a tree rather than a single line. Thus, accurate simulation and efficient calculation of propagation delay for interconnect trees are critical to performance driven synthesis and layout [1].
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